The present invention relates to a method and apparatus for operating a flash memory cell.
Flash memory is a variety of electronic memory in which a specialized field effect transistor is used to store a data value. A binary data value is represented by programming the transistor to have one of two threshold voltage values. Like EEPROM, the threshold voltage value of a Flash memory transistor is programmable by storing and releasing charge on a floating gate structure within the transistor. Unlike EEPROM Flash memory includes a mechanism by which a large number of memory cells may be erased simultaneously. Also, the tunnel oxide layer between a floating gate and a channel region of a Flash memory cell transistor is typically thinner and more uniform than the corresponding oxide layer between the floating gate and channel region of an EEPROM memory cell transistor.
The foregoing will be more fully explained with reference to FIG. 1 which illustrates a structure of an n-channel flash memory transistor 100 including a source 102 of n-doped semiconductor material, a drain 104 of n-doped semiconductor material, a first insulating layer 106, a floating gate structure 108, a second insulating layer 110, and a control gate structure 112. The first and second insulating layers are formed of, for example, silicon dioxide. The floating gate and control gate structures are formed of, for example, poly-crystalline silicon (poly).
The transistor 100 is formed in a doped region 114 (e.g., a p-well) of a substrate 116. The p-well includes a channel region 118 under the first insulating layer 106. The substrate 116 includes a semiconductor material such as single-crystal silicon. The p-well 114 is bounded at a lower boundary by an implanted region of n-type material 120, and at a perimeter 122 by a trench of diffusion-doped n-type material 124.
The transistor 100 is programmed into a particular state by varying an amount of charge stored on the floating gate structure 108. The state of the transistor is then read by applying a voltage between the drain 104 and source 102 of the transistor and sensing a resulting magnitude of current through the transistor.
In one exemplary flash memory transistor, the floating gate 108 is made of conductive (doped semiconductor) material but is not directly connected to an external source of charge. Charge is added to and removed from the floating gate by injection and tunelling across the first insulating layer 106. Various mechanisms for charge transfer are known in the art. For example, charge may be added to the floating gate 108 by Channel Hot Electron Injection, and removed from the floating gate 108 by Fowler-Nordheim tunnelling.
In Channel Hot Electron Injection, electrons are accellerated to high velocities by high strength electric fields. These xe2x80x9cballisticxe2x80x9d electrons are then propelled by the high fields from the source 102 into the insulating material 106. A certain proportion of the ballistic electrons traverse the insulator 106 without scattering, and are captured in the floating gate 108 material on the other side. These captured electrons act to increase the quantity of charge on the floating gate 108.
Fowler-Nodheim (F-N) tunneling depends on the fact that, per quantum mechanics, there is a finite probability that a particle will traverse an energy barrier of finite height, despite the fact that the energy of the particle is insufficient to surmount the energy barrier. Once an electron tunnels from the floating gate 108 into the first insulating layer 106, it can move freely in the valence or conduction band of the insulator 106 and may thus traverse the insulator. As electrons tunnel out of the floating gate 108, the charge on the floating gate diminishes. The currents resulting from both Hot Electron Injection and F-N tunneling depend on the respective potentials of the flash transistor source 102, drain 104, and control gate 112.
A first quantity of charge is introduced onto the floating gate structure 108 during an erase operation. To cause this transfer of charge to the floating gate 108, the source 102 and p-well 114 of the transistor 100 are raised to a high potential such as approximately 9V. This erases the transistor 100 and establishes a first state of the transistor (e.g. a logical zero state). Thereafter, if it is desired to program the transistor to represent a logical one state, the quantity of charge present on the floating gate structure 108 is modified. This is done by applying a potential within a particular range of potentials between the control gate structure and the source and drain of the transistor. Consequently, some electrons tunnel out of the floating gate 108, across the insulator 106, and a second quantity of charge is left on the floating gate structure 108.
The quantity of charge on the floating gate affects the operation of the transistor. Depending on the characteristics of the transistor, the charge on the floating gate may supplement or oppose the effect of a sensing voltage applied to the control gate. For example, in an enhancement mode n-mos transistor, the presence of charges (electrons) on the floating gate attracts holes into the channel region of the transistor and increases its conductivity. Thus, a transistor with a highly charged floating gate exhibits a lower turn-on threshold voltage (Vth) than the same transistor with its floating gate relatively discharged.
Alternately, depending on transistor polarity, the charge stored on the floating gate structure shields the channel region below that gate from the fields of charges introduced into the control gate, and inhibits the accumulation of free carriers within the channel region. Therefore, the threshold voltage of the transistor is again modified by the presence of charge on floating gate.
When exemplary transistor 100 is in an erased state (e.g. programmed to represent a logical zero) the threshold voltage of the transistor is relatively low, and the channel 118 becomes conductive when a sensing voltage is applied to the control gate 112 of the transistor. Conversely, when transistor 100 is programmed to a logical one and a sensing voltage is applied to the control gate 112 of the transistor, the channel 118 remains non-conductive. Thus, substantially no current flows through the transistor between the column line and the array ground node in response to an applied source-drain voltage.
As shown in FIG. 2 a flash memory device 200 includes a plurality of memory transistors 100 arranged in a two-dimensional array 202. Along a first dimension of the two dimensional array, the transistors 100 form rows as shown by 204.
Along a second dimension of the two dimensional array, the transistors 100 form columns as shown by 206. The device includes a plurality of conductive traces (row lines) 208 (otherwise denominated word lines) disposed along the rows respectively. Each row line 208 is coupled to the respective control gates 112 of the transistors 100 of the respective row 204. Thus the control gate 112 of every transistor of a row quickly assumes an electrical potential (i.e., a sensing voltage) impressed on the respective row line 208 of the row.
The device 200 also includes a plurality of column lines 210 (otherwise denominated bit lines) disposed along respective columns 206 of transistors 100. Each column line is coupled to the respective drain 104 of the transistors 100 of a respective column.
The source of every transistor is coupled to an electrical node designated array ground 212 through a plurality of array ground lines 214. As will be discussed further below, the array ground node is switchingly connectable, by means of a switching device 216, to a source of reference potential (e.g. ground potential) 218.
As seen in FIG. 2, the array 202 of memory cell transistors 100 is disposed in P-well 114, the perimeter of which is bounded by N-well 124. The device 200, including the n-well, is disposed in p-type substrate 116. A plurality of sense amplifiers 220, each having an input 222 coupled to a respective one of the plurality of column lines 210 are disposed in the p-type substrate outside of the p-well 114.
An erase potential switching device 234 switchingly couples a source of an erase voltage VErs 236 to the p-well 114. A further switching device (transistor) 235 is disposed to switchingly couple a source of the erase potential switching device to the plurality of array ground lines 214. When activated by a signal at an input 238, the switching device acts to raise the potential of the p-well 114 to VErs (e.g., 9V) as part of the device erasure cycle. Concurrently, the switching device 235 becomes conductive, coupling the array ground lines 214 to the source of erase voltage VErs through the erase potential switching device 234. Subsequent to device erasure, the erase potential switching device 234 becomes non-conductive, and a grounding switching circuit 240 switchingly couples the p-well 114 to a source of ground potential 218.
The circuit of FIG. 2 functions as a wired-or device. During a read cycle, a potential (e.g., Vcol) 232 is applied to each of the column lines 210 through a pull-up resistor 230. Also during the read cycle, one of the plurality of rows is selected based on an output received from a conventional row decoder. Consequently, the row line (word line) 208 of the selected row is raised from a first low potential (e.g. ground) to a sensing voltage. The sensing voltage lies between the threshold voltage of an erased cell and the threshold voltage of a programmed cell. The sensing voltage is transferred to the respective control gate 112 of each transistor 100 of the row 204. If the sensing voltage is above the threshold voltage for a particular transistor, as programmed, the transistor will become conductive. Otherwise, the transistor will be non-conductive. Thus, depending on the programmed state (erased/programmed) of each transistor of the row, that transistor may or may not short the column line 210 to which it is connected to the array ground line 214. If the transistor becomes conductive when the sensing voltage is applied, it causes the column line 210 to which the transistor 100 is coupled to drop to the potential of the array ground line 214. Otherwise, the column line remains at approximately Vcol 232. In either case, the voltage of the column line is sensed by a sensing circuit 220 and output to an output line 221. The outputs of the sensing circuits, taken together, form an output word corresponding to the data values stored in the selected row of the flash memory device.
Depending on the number of erased and programmed memory cells in an output word, the current delivered to the array ground line 214 by the flash memory transistors 100 may be large or small. In the extreme case where every memory cell of the row has been programmed to a 1 state, all transistors remain non-conductive when the sensing voltage is applied to the respective control gates 112 of the transistors 100. Thus, essentially no current is conducted to the array ground line. At the other extreme, when every memory cell of the row remains in its erased state, a maximum (worst case) current is delivered to the array ground line.
As previously noted, the array ground line is coupled to ground through a switching device such as a transistor 216. This is necessary so that the array ground may be decoupled from ground potential during an erase cycle. In order to conduct the worst case array ground current without unduly raising the voltage of the array ground line, the transistor 216 and array ground traces 214 must be made large. If the transistor 216 and array ground lines 214 are not sufficiently conductive, and the voltage on the array ground line 214 rises, then the voltage differential across the source and drain of the flash memory transistors is reduced.
In practice during a read cycle, conventional array ground lines may experience a voltage rise (and hence a reduction in source-drain voltage). Because the column lines 210 are capacitive, this reduction in source-drain voltage increases the time required for the column lines to discharge to a stable output potential. In other words, device operation is slower under worst case conditions, as described.
If device operation is slowed, the device may miss a timing window i.e. not reach a stable voltage before an output state of the device is read by a further system to which the Flash memory device is coupled. In such a case, a spurious value may be transferred to the further system.
Also, threshold voltage Vth of the flash memory transistor 100 is referenced to the source 102 of the transistor 100, which is coupled to the array ground line 214. The sensing voltage (applied to the control gate 112 via the row line 208), however, is referenced to the p-well 114. Thus as the array ground line 214 voltage rises with respect to the p-well 114, the apparent voltage applied to the control gate 112 is reduced. The conductivity of the flash memory transistor 110 may diminish responsively, further slowing device response. Moreover, if the array ground line voltage is driven up far enough, an erased transistor would be shut off entirely, again resulting in spurious data output.
Accordingly, it is desirable to have a flash memory device adapted to rapidly and reliably output data in response to a read command even when a large proportion of the transistors of a row being read are programmed to a conductive state.
The invention provides a distributed switchable coupling (typically a transistor) between the array ground line and the p-well. This coupling prevents the electrical potential of the array ground line from rising far above the electrical potential of the p-well. In one aspect of the invention, a distributed transistor is disposed within the p-well having a first (drain) terminal coupled to the array ground line and a second (source) terminal coupled to the p-well. In another aspect of the invention, a plurality of transistors distributed throughout the p-well and adapted to switchingly couple the array ground node to the p-well in which the array of flash memory transistors is disposed. The p-well is adapted to be switchingly coupled to a source of high voltage during an erase cycle and otherwise to a source of ground potential.
The method and apparatus of the invention can be applied to a flash memory device having plural banks of memory arrays, each bank having a respective plurality of array ground lines, each array ground line having a respective plurality of coupling transistors.